The present invention relates to a semiconductor integrated circuit device and a method of producing the same, specifically to a technique effective in application to a DRAM (Dynamic Random Access Memory) in which the bit lines of small line widths are formed with a conductive film containing W (tungsten) as the principal component.
The memory cells of a DRAM are arranged at the intersections of plural word lines and plural bit lines that are arrayed in a matrix on the principal plane of a semiconductor substrate. The memory cell is composed of one memory cell selecting MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one data storing capacitor connected in series to the MISFET.
The memory cell selecting MISFET is mainly composed of a gate oxide film, a gate electrode integrated with a word line, and a pair of semiconductor areas that form the source and drain thereof. The data storing capacitor is laid out over the memory cell selecting MISFET, and is electrically connected to one of the source and drain of the memory cell selecting MISFET. Also, the bit line is laid out over the memory cell selecting MISFET, and is electrically connected to the other one of the source and drain.
The DRAM adopting the so-called stacked capacitor structure that arranges the data storing capacitors to overlie the memory cell selecting MISFETs adopts the Capacitor Over Bit-line (COB) structure that arranges the data storing capacitors to overlie the bit lines.
The bit lines of the DRAM having memory cells of the COB structure are formed on the same process as that of the first layer wirings of the peripheral circuits, and accordingly a low resistance metal containing the tungsten as the principal component is used as a bit line material. The DRAM in which the bit lines are formed with a metal film having the tungsten as the principal component is disclosed in, for example, the Japanese Published Unexamined Patent Application No.Hei 7(1995)-122654, and corresponding U.S. Pat. No. 5,604,365, etc.
The inventor has been concentrating the energies on further fining the COB structured DRAM that arranges the data storing capacitors over the bit lines.
In the COB structured memory cells, one of the sources and drains of the memory cell selecting MISFETs are connected with the data storing capacitors by way of through holes passing between the adjoining bit lines. Therefore, to reduce the memory cell size needs to reduce the pitch between the bit lines, and it becomes difficult to ensure the joint margin of the bit lines and the through holes passing between them. Accordingly, there occurs a problem that the plugs embedded inside the through holes can short-circuit the bit lines.
To avoid such deficiencies, it is necessary to make the bit lines as fine as possible, and the inventor has been investigating to introduce the so-called Damascene process as a measure for fining the bit lines, that embeds a conductive film serving as a bit-line material inside the wiring grooves formed on an insulating film.
In order to form the bit lines, this method first forms the wiring grooves by etching a silicon oxide film deposited on the memory cell selecting MISFETs. The wiring grooves are formed in the minimum size that is determined by the resolution limit of the photolithography. Next, the method deposits a second silicon oxide film having a thickness less than half the width of the wiring grooves, on the silicon oxide film including the insides of this wiring grooves, and forms side wall spacers composed of the second silicon oxide film on the side walls of the wiring grooves, by applying an anisotropic etching onto the second silicon oxide film. Since the width of the wiring grooves is equal to the minimum size that is determined by the resolution limit of the photolithography, the inside width of the side wall spacers becomes smaller than this minimum size. After depositing so thick a tungsten film as to completely bury the insides of the wiring grooves on the silicon oxide film including the insides of the wiring grooves, the method removes the tungsten film over the silicon oxide film by means of a chemical and mechanical polishing to leave the tungsten film only insides the wiring grooves.
Since the bit lines formed by the above method achieves the width narrower than the minimum size determined by the resolution limit of the photolithography, the joint margin of the adjoining bit lines and the through holes passing between them can be attained sufficiently, so that the memory cell size can be reduced.
Now, the bit lines BL formed by the above method produce local strippings on the boundary faces with the side wall spacers when the width of the bit lines is 1 xcexcm or less. They further produce overall strippings on almost all over the areas of the wiring grooves when the width becomes narrower than 0.2 xcexcm, which leads to disconnections as a result, which was found through the examinations by the inventor.
The present invention has been made in view of the above circumstances, and it is therefore an object of the invention to provide a technique that effectively prevents the disconnections when fining the width of the wirings composed of the tungsten as the principal component.
Another object of the invention is to provide a technique to reduce the memory cell size, by making the width of the bit lines as fine as less than the minimum processing size that is determined by the resolution limit of the photolithography.
Another object of the invention is to provide a technique that improves the detection sensitivity of signals stored in the data storing capacitors, by reducing parasitic capacitances along the bit lines of a DRAM.
The foregoing and other objects and the novel features of the invention will become apparent from the descriptions and accompanying drawings of this specification.
In the semiconductor integrated circuit device according to one aspect of the invention, wiring grooves are formed on a first insulating film formed on a principal plane of a semiconductor substrate, side wall spacers composed of a second insulating film are formed on the side walls of the wiring grooves, wirings containing the tungsten as a principal component are formed on the regions inside the side wall spacers, and an adhesive layer composed of a conductive film having a higher adhesive strength to the second insulating film than the tungsten is formed on the boundary faces between the side wall spacers inside the wiring grooves and the wirings.
Further, the method of producing the semiconductor integrated circuit device according to the invention includes the following processes:
(a) forming the wiring grooves on the first insulating film on the principal plane of the semiconductor substrate, depositing the second insulating film having such a film thickness that does not completely buries the insides of the wiring grooves on the first insulating film including the insides of the wiring grooves, and then forming the side wall spacers composed of the second insulating film on the side walls of the wiring grooves, by applying an anisotropic etching to the second insulating film,
(b) depositing a second conductive film having such a film thickness that does not completely buries the insides of the wiring grooves, which has a higher adhesive strength to the second insulating film than the tungsten, on the first insulating film including the insides of the wiring grooves, then depositing a first conductive film containing the tungsten as the principal component on the second conductive film including the insides of the wiring grooves, and embedding the insides of the wiring grooves with the first conductive film, and
(c) forming first wirings composed of the first conductive film inside the wiring grooves, by polishing the first conductive film and the second conductive film chemically and mechanically to remove the first conductive film and the second conductive film that lie outside the wiring grooves.
According to the foregoing means, the second conductive film having a higher adhesive strength to the second insulating film than the tungsten functions as the adhesive layer that prevents strippings on the boundary faces between the first wirings and the side wall spacers; and accordingly the disconnections of the first wirings can effectively prevented in case of the wirings being fined.